Reducing Leakage Power for SRAM Design Using Sleep Transistor
نویسندگان
چکیده
منابع مشابه
8T SRAM Cell Design for Dynamic and Leakage Power Reduction
This paper addresses a, novel eight transistor (8T) CMOS SRAM cell design to enhance the stability and to reduce dynamic and leakage power. For the validation of proposed 8T SRAM cell, compared results with reported data. The parameters used in the proposed cell are comparable to the existing 8T SRAM cell at same technology and design rules. The stability of the proposed cell has been analyzed ...
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ژورنال
عنوان ژورنال: Acta Physica Polonica A
سال: 2013
ISSN: 0587-4246,1898-794X
DOI: 10.12693/aphyspola.123.185